1. Field of the Invention
This invention relates to the field of semiconductor device fabrication. Specifically, it applies to the field of patterning selected layers during the fabrication.
2. Prior Art
In the early years of metal oxide semiconductor (MOS) technology, resistance elements for integrated circuits were provided by diffused regions in the substrate, polysilicon members, and the like. These elements, which occupied relatively large areas in the circuit, are not as widely used with the advent of more complex circuitry which require higher densities and higher resistances.
The lack of adequate resistors for use in high density semiconductor integrated circuits (IC's) led to an avoidance of their use. Circuits were deliberately designed to use fewer resistors, and in many cases transistors were used in their place. The static memory cell, for instance, has traditionally been constructed as a six transistor bistable circuit in which two of the six transistors serve as load devices.
Recently, advances have been made in the use of vertical load resistors composed of silicon-rich silicon nitride type films. By applying the resistors vertically, area on the semiconductor wafer is conserved, making resistance elements feasible in complex high density circuitry. Unfortunately, prior art techniques for patterning silicon nitride or silicon films do not work well for patterning vertical resistors on high-density semiconductor devices.
As disclosed in the patent application entitled, Plasma Enhanced Chemical Vapor Deposited Vertical Resistor; Ser. No. 825,314; filed Feb. 3, 1986, and assigned to the assignee of the present invention, it is often desirable to layer vertical resistors over areas near shallow transistor junctions composed of N+ or P+ doped silicon, then to remove a layer from selected junctions, wherein leaving the layer over other areas. Prior art chemical vapor deposition (CVD) techniques do not damage these delicate shallow regions. However, dry plasma etching of the resistive layer can damage the shallow juntions because the etching is not sufficiently selective. The plasma begins etching the shallow junction before the resistive layer is completely removed. Wet etching also causes problems. First, photoresist will not survive an attack by available wet etch solutions, which can selectively etch the vertical load resistor over underlying dielectric or silicon layer. Second, other available wet etch solutions do not selectively etch vertical load resistors and also attack the underlying layers. Third, because wet etching does not work anisotropically, it tends to undercut exposed layers.
The present invention avoids all these problems. It is particularly useful in the fabrication of vertical load resistors for MOS static random access memory (SRAM) devices; however, it may be practiced in most any semiconductor device fabrication.